1. Field
This document relates to a liquid crystal display device which can reduce the number of output channels of a data driving circuit.
2. Related Art
An active matrix driving type liquid crystal display displays moving pictures by using a thin film transistor (hereinafter, “TFT”) as a switching element. Since such LCDs can be made smaller than cathode ray tubes, they have been applied to various displays of mobile information devices, office machines, computers, televisions, etc. Liquid crystal cells of a liquid crystal display displays picture images by changing transmittance according to a potential difference between a data voltage supplied to a pixel electrode and a common voltage supplied to a common electrode.
Measures for changing the connection configuration of liquid crystal cells of a liquid crystal display panel are continuously being implemented to reduce the number of output channels of a data driving circuit in a liquid crystal display device. FIG. 1 shows the comparison between a typical normal panel and a double rate driving (DRD) panel for reducing the number of output channels.
The normal panel as shown in (A) of FIG. 1 realizes a horizontal resolution of 800 using 2400 (800*3(RGB)) data lines DL. Since output channels of the data driving circuit are connected to the data lines DL in one-to-one correspondence, the data driving circuit for driving the normal panel requires 2400 output channels.
The DRD panel as shown in (B) of FIG. 1 can realize a horizontal resolution of 800 using only 1200 data lines DL because a pair of adjacent left and right liquid crystal cells with a data line DL interposed therebetween shares the data line DL. That is, the pair of liquid crystal cells sharing the same data line DL are adjacent in an extension direction of the gate lines. Accordingly, the number of output channels of the data driving circuit for driving the DRD panel is reduced to 1200 which is half the number of output channels shown in (A) of FIG. 1.
However, the DRD panel has a panel rendering structure in which the liquid crystal cells sharing the data line DL receive data in a time-division manner. Thus, a timing controller has to change an alignment sequence of video data in accordance with this panel rendering structure. This will be explained concretely with reference to FIG. 2.
In general, the input sequence of video data input to the timing controller from a system board is in agreement with the normal panel rendering structure as shown in (A) of FIG. 1. In this case, the timing controller synchronizes the output sequence of the video data with the input sequence thereof from the system board as shown in (A) of FIG. 2. That is, the timing controller outputs video data for one horizontal line to the data driving circuit in the order of R0, G0, B0, R1, G1, B1, . . . , R799, G799, B799.
On the other hand, in the DRD panel rendering structure as shown in (B) of FIG. 1, the writing sequence of video data is in accord with the illustrated arrow directions. Thus, the timing controller has to align video data input from a system in the order of R0, G0, B0, R1, G1, B1, . . . R799, G799, B799 in accordance with the data writing sequence indicated by the arrow directions. The timing controller time-divides 1 horizontal period for applying video data for 1 horizontal line, and respectively aligns pre-charge data for ½ horizontal line to be written first in the order and post-charge data for ½ horizontal line to be written later in the order. The timing controller aligns the pre-charge data in the order of R0, R1, B1, R2, R3, B3, . . . R796, R797, B797, R798, R799, B799, and then outputs the pre-charge data to the data driving circuit in this alignment sequence during the first half of the horizontal period. The pre-charge data comprises all the red (R) data R0, R1, R2, R3, . . . R796, R797, R798, R799, and one half odd-numbered blue (B) data B1, B3, B797, B799, both of which are to be written within the one horizontal period. The timing controller aligns the post-charge data in the order of G0, B0, G1, G2, B2, G3, . . . , G796, B796, G797, G798, B798, G799, and then outputs the post-charge data to the data driving circuit in this alignment sequence during the second half of the horizontal period. The post-charge data comprises all the green (G) data G0, G1, G2, G3, . . . G796, G797, G798, G799 and the other half even-numbered blue (B) data B0, B2, . . . B796, B798, both of which are to be written within the horizontal period.
As such, a liquid crystal display device having a DRD panel necessarily requires a line memory for storing input video data for each horizontal line as shown in FIG. 3 because the alignment sequence of video data has to be changed in accordance with the panel rendering structure. This causes cost increase.